This invention relates generally to logic circuits and more particularly to an integrated NAND and flip-flop circuit.
Digital signal processors (DSPs) are becoming increasingly important in today""s society, being used with many common place devices. DSPs are utilized in cell phones, personal digital assistance, appliances, and many other devices. Digital signal processors perform different functions, depending upon the type of device in which it is used. However, all digital signal processors utilize logic circuits.
Logic circuits receive an input and produce an output based on a set of specified criteria. Logic circuits are generally formed from a plurality of logic gates. Example logic gates includes AND, NAND, OR, and XOR. Logic circuits are designed to allow data to flow as rapidly as possible, but sometimes it is desirable to hold a state of an input to, or output from, a logic circuit. One way of holding the state of a particular inputs, or variable, is though the use of a flip-flop. Flip-flops are logic circuits that hold the state of a variable for a desired time period.
Requirements for faster DSPs create the desire to build DSPs that can operate at a higher clock frequency. The clock speed of DSPs is limited by the number of gates in a critical path. In other words, data can progress through only so many gates within a single clock cycle. If the number of gates is decreased, then the clock speed can be increased because less time is required to progress through the gates. Therefore, it is desirable to decrease the number of gates in logic circuits whenever possible. Removing even just one gate is considered important in today""s DSPs.
Flip-flops generally utilize a series of inverters connected to transmission gates, usually starting with an inverter and ending with an inverter. A flip-flop often creates a critical path in a logic circuit. Therefore it is desirable to reduce the number of gates in flip-flops to as few as possible.
Accordingly, a need has arisen for an integrated NAND in flip-flop circuits. The present invention provides an apparatus that addresses shortcomings of prior systems and methods.
According to one embodiment of the invention, a combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate. The plurality of signals comprises signals indicative of a first data signal, a second data signal, a scan-in signal, and a scan-enable signal. These circuits include a NAND gate having first and second inputs operable to receive the first and second output signals of the pre-NAND scan circuit. They also include a first transmission gate and a first inverter. The transmission gate receives the output of the NAND gate and the inverter receives the output of the transmission gate. The pre-NAND scan circuit is operable to produce the first and second output signals based on the plurality of input signals such that the first and second output signals are defined as described below. When the scan-enable signal is equal to a logical one then the first output signal and the second output signal are either both equal to the scan-in signal or the first output signal is equal to a logical one and the second output signal is equal to the scan-in signal. When the scan-enable signal is equal to a logical zero, then the first output signal is equal to the first data signal and the second output signal is equal to the second data signal.
Some embodiments of the invention provides numerous technical advantages. For example, some embodiments of the invention allow reduction of the number of gates along a critical timing path in a flip-flop, resulting in a faster flip-flop and therefore faster DSPs. Such reduction in the number of gates can occur without any significant additional processing steps.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.